Creating evaluation hardware using a high level modeling system

ABSTRACT

Within a system comprising a processor and a memory, a method of creating evaluation hardware within an integrated circuit can include automatically inserting, by the processor, a disable circuit block into a circuit design. The method can also include automatically selecting a location within the circuit design to insert the disable circuit block, and/or inserting an unlock circuit block into the circuit design, wherein responsive to receiving an unlock code, the unlock circuit block overrides the disable circuit block. The method also can include storing, within the memory, the circuit design comprising the disable circuit block.

FIELD OF THE INVENTION

The embodiments disclosed within this specification relate to integratedcircuit devices (ICs). More particularly, the embodiments relate tocreating evaluation hardware for an IC using a high level modelingsystem.

BACKGROUND

A high level modeling system (HLMS) is a computer-based, circuit designtool that allows a user to create a circuit design at a high level ofabstraction. An HLMS provides a design environment within which the usercreates circuit designs using a modular approach. Typically, the HLMSprovides a graphic design environment in which circuit blocks areinserted into the circuit design using a “drag-and-drop” designparadigm, though command line options are usually available as well. Theuser can drag circuit blocks, represented as graphic blocks, into thedesign environment. Each circuit block can represent a particularcircuit function such as multiplexing, addition, multiplication,filtering, or the like. The user also can specify connectivity andsignal flows within the circuit design by coupling exposed ports ofcircuit blocks by drawing lines, representing wires, coupling the ports.The user effectively builds an electronic circuit design by constructinga block diagram.

In addition to being used to create user-specified circuit designs, anHLMS can be used by a provider of intellectual property (IP) to generatecircuit designs that can be licensed to third parties. To facilitate thelicensing process, it is necessary for the IP provider to make a versionof the circuit design available to potential licensees for evaluation.Typically, protective mechanisms are placed into the circuit design bythe provider to prevent potential licensees from having unfettered useof the circuit after expiration of a trial period. At the conclusion ofthe trial period, with the circuit design being implemented in hardwareas a circuit, the protective mechanism typically renders the circuitunusable.

Creation of an evaluation version of a circuit design is a manualprocess that can be both time consuming and complicated. The designermust manually incorporate the protective mechanisms within the circuitdesign to be evaluated and make any necessary signal connections ormodifications.

SUMMARY

The embodiments disclosed within this specification relate to integratedcircuit devices (ICs). More particularly, the embodiments relate tocreating evaluation hardware for an IC using a high level modelingsystem. One embodiment of the present invention can include a method ofcreating evaluation hardware within an integrated circuit using a systemcomprising a processor and a memory. The method can includeautomatically inserting, by the processor, a disable circuit block intoa circuit design and storing, within the memory, the circuit designcomprising the disable circuit block.

The method can include selecting the disable circuit block to specify anelectronic circuit that passes a received signal as an output signalwhile a number of received clock cycles does not exceed a threshold andoutputs a static disable signal when the number of received clock cyclesexceeds the threshold.

Automatically inserting can include automatically selecting a locationwithin the circuit design to insert the disable circuit block. In oneaspect, automatically inserting can include selecting at least one clockenable signal within the circuit design and inserting the disablecircuit block on each selected clock enable signal within the circuitdesign. In another aspect, automatically inserting can include selectingat least one of an input port or an output port within the circuitdesign and inserting the disable circuit block on each selected port.

Automatically inserting further can include selecting a reset signal forat least one circuit element that stores state within the circuit designand inserting the disable circuit block on each reset signal. In stillanother aspect, automatically inserting can include sorting nets of thecircuit design according to fanout, selecting a predetermined number ofnets with highest fanout, and inserting the disable circuit block on atleast one signal of each selected net.

An unlock circuit block also can be inserted into the circuit design.Responsive to receiving an unlock code, the unlock circuit block canoverride the disable circuit block.

Another embodiment of the present invention can include a system thatcreates evaluation hardware. The system can include a memory storingprogram code and a processor coupled to the memory and executing theprogram code. The processor can perform executable steps includingautomatically inserting a disable circuit block into the circuit designand storing, within the memory, the circuit design comprising thedisable circuit block.

The processor further can perform an executable step including selectingthe disable circuit block to specify an electronic circuit that passes areceived signal as an output signal while a number of received clockcycles does not exceed a threshold and outputs a static disable signalwhen the number of received clock cycles exceeds the threshold.

The processor can perform an executable step including automaticallyselecting a location within the circuit design to insert the disablecircuit block. Automatically inserting can include selecting at leastone clock enable signal within the circuit design and inserting thedisable circuit block on each selected clock enable signal within thecircuit design. In another aspect, automatically inserting can includeselecting at least one of an input port or an output port within thecircuit design and inserting the disable circuit block on each selectedport.

Automatically inserting also can include selecting a reset signal for atleast one circuit element that stores state within the circuit designand inserting the disable circuit block on each reset signal. In stillanother aspect, automatically inserting can include sorting nets of thecircuit design according to fanout, selecting a predetermined number ofnets with highest fanout, and inserting the disable circuit block on atleast one signal of each selected net.

Another embodiment of the present invention can include a devicecomprising a data storage medium usable by a system comprising aprocessor and a memory. The data storage medium can store program codethat, when executed by the system, causes the system to executeoperations. The operations can include automatically inserting a disablecircuit block into the circuit design and storing, within the memory,the circuit design comprising the disable circuit block.

Automatically inserting can include selecting at least one clock enablesignal within the circuit design and inserting the disable circuit blockon each selected clock enable signal within the circuit design. Inanother aspect, automatically inserting can include selecting at leastone of an input port or an output port within the circuit design andinserting the disable circuit block on each selected port.

Automatically inserting further can include selecting a reset signal forat least one circuit element that stores state within the circuit designand inserting the disable circuit block on each reset signal. In stillanother aspect, automatically inserting can include sorting nets of thecircuit design according to fanout, selecting a predetermined number ofnets with highest fanout, and inserting the disable circuit block on atleast one signal of each selected net.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a first block diagram illustrating a high level modelingsystem for generating an electronic system in accordance with oneembodiment of the present invention.

FIG. 2 is first listing of program code illustrating a port interface ofa disable circuit block in accordance with another embodiment of thepresent invention.

FIG. 3 is second listing of program code illustrating an architecturaldescription of a disable circuit block in accordance with anotherembodiment of the present invention.

FIG. 4 is a second block diagram illustrating an unlock circuit block inaccordance with another embodiment of the present invention.

FIG. 5 is block diagram of an evaluation circuit design in accordancewith another embodiment of the present invention.

FIG. 6 is a flow chart illustrating a method of creating an evaluationversion of a circuit design in accordance with another embodiment of thepresent invention.

DETAILED DESCRIPTION

While the specification concludes with claims defining the features ofthe embodiments of the invention that are regarded as novel, it isbelieved that the embodiments of the invention will be better understoodfrom a consideration of the description in conjunction with thedrawings. As required, detailed embodiments of the present invention aredisclosed herein; however, it is to be understood that the disclosedembodiments are merely exemplary of the inventive arrangements, whichcan be embodied in various forms. Therefore, specific structural andfunctional details disclosed herein are not to be interpreted aslimiting, but merely as a basis for the claims and as a representativebasis for teaching one skilled in the art to variously employ theinventive arrangements in virtually any appropriately detailedstructure. Further, the terms and phrases used herein are not intendedto be limiting, but rather to provide an understandable description ofthe embodiments of the invention.

The embodiments disclosed within this specification relate to integratedcircuit devices (ICs). More particularly, the embodiments relate tocreating evaluation hardware for an IC using a high-level modelingsystem (HLMS). In accordance with the inventive arrangements disclosedwithin this specification, an HLMS can be configured to automaticallyinsert a disabling mechanism into a circuit design to generate anevaluation version of the circuit design. In one aspect, the type ofdisabling mechanism can be selected in addition to the particularlocation within the circuit design at which the disabling mechanism isto be placed. The HLMS can automatically insert the disabling mechanismand establish any necessary signal couplings.

The resulting circuit design, comprising the disabling mechanism, can beoutput and stored as an evaluation version of the circuit design. Whenthe circuit design is ultimately instantiated or otherwise createdwithin an IC as hardware, the circuit specified by the evaluationcircuit design will be disabled according to the particular process ortechnique utilized by the disabling mechanism inserted therein. Thus,the evaluation circuit design, when implemented in hardware, will onlyoperate in accordance with the restrictions and/or limitationsimplemented by the disabling mechanism.

FIG. 1 is a first block diagram illustrating an HLMS 100 for generatingan electronic system in accordance with one embodiment of the presentinvention. In one aspect, HLMS 100 can generate one or more circuitdesigns for instantiation within, or implementation as, an IC. Thecircuit designs that are generated can be instantiated within an IC,whether the IC is programmable or not. In generating circuit designs,HLMS 100 can insert a disabling mechanism in the form of one or moredisable blocks within the circuit design to create an evaluation circuitdesign.

Programmable ICs are a well-known type of IC that can be programmed toperform specified logic functions. Examples of programmable ICs caninclude, but are not limited to, field programmable gate arrays (FPGAs),complex programmable logic devices (CPLDs), and mask programmabledevices. The phrase “programmable IC” refers to the ICs noted herein andICs that are only partially programmable. For example, another type ofprogrammable IC includes a combination of hard-coded transistor logicand a programmable switch fabric that programmably interconnects thehard-coded transistor logic.

Some types of programmable ICs, such as FPGAs and CPLDs, are programmedby providing data bits to the device for the purpose of configuring thedevice. The programmable IC is configured, by loading the data bits, toimplement or instantiate a particular electronic system or circuitspecified by the data bits. The data bits provided to the programmableIC for the purpose of configuration also can be referred to asconfiguration data and, in some cases, a bitstream.

Turning again to FIG. 1, HLMS 100 can include at least one processor 105coupled to memory elements 110 through a system bus 115. As such, HLMS100 can store program code within memory elements 110. Processor 105 canexecute the program code accessed from memory elements 110 via systembus 115. In one aspect, for example, HLMS 100 can be implemented as acomputer that is suitable for storing and/or executing program code. Itshould be appreciated, however, that HLMS 100 can be implemented in theform of any system comprising a processor and memory that is capable ofperforming the functions described within this specification.

Memory elements 110 can include one or more physical memory devices suchas, for example, local memory and one or more bulk storage devices.Local memory refers to random access memory or other non-persistentmemory device(s) generally used during actual execution of the programcode. Bulk storage device(s) can be implemented as a hard drive or otherpersistent data storage device. System 100 also can include one or morecache memories that provide temporary storage of at least some programcode in order to reduce the number of times program code is retrievedfrom the bulk storage device during execution.

Input/output (I/O) devices such as a keyboard 130, a display 135, and apointing device (not shown) optionally can be coupled to HLMS 100. TheI/O devices can be coupled to HLMS 100 either directly or throughintervening I/O controllers. Network adapters also can be coupled toHLMS 100 to enable HLMS 100 to become coupled to other systems, computersystems, remote printers, and/or remote storage devices throughintervening private or public networks. Modems, cable modems, andEthernet cards are examples of different types of network adapters thatcan be used with HLMS 100.

As pictured in FIG. 1, memory elements 110 can store program code in theform of a high level circuit design application (design application)140. Design application 140, being implemented in the form of executableprogram code, causes processor 105 to perform the functions describedwithin this specification and enables functionality of HLMS 100. Ingeneral, design application 140 can be used to specify an electronicsystem, such as a circuit design, at a high level of abstraction. Designapplication 140 can provide the instructions necessary to implement thedesign environment that is characteristic of an HLMS, in general, andthus, facilitates block level circuit design where each block representsa circuit function.

In operation, a circuit design 145 can be loaded into HLMS 100. HLMS100, executing design application 140, can select a disable circuitblock 150 from a library 155 of circuit blocks. Library 155 can includea variety of different circuit blocks including a plurality of differenttypes of disable circuit blocks available for inclusion within circuitdesigns. It should be appreciated that while library 155 is illustratedas being stored within memory elements 110, library 155 also can bestored within a remote data storage device, within a different computersystem, etc. Library 155 is shown as being stored within memory elements110 for purposes of illustration.

Design application 140, having selected disable block 150, can insertdisable block 150 into circuit design 145. Accordingly, the resultingcircuit design, denoted as evaluation circuit design 160, can be outputand stored within memory elements 110. Evaluation circuit design 160 is,in general, circuit design 145 with disable circuit block 150 includedtherein. Design application 140 can automatically insert disable circuitblock 150 into circuit design 145 and establish and/or create anynecessary signal couplings to effectuate the inclusion of disablecircuit block 150 into circuit design 145.

Disable circuit block 150 can specify the hardware, e.g., circuitry, andsignals that disable circuit design 145. In one embodiment, for example,disable circuit block 150 can specify hardware description languagedefining a particular implementation of the disable mechanismrepresented by disable circuit block 150.

FIG. 2 is first listing of program code illustrating a port interface200 of a disable circuit block in accordance with another embodiment ofthe present invention.

FIG. 2 illustrates an embodiment in which the disable circuit blockselected for inclusion within the circuit design specifies a hardwaredescription language (HDL), e.g., VHDL, implementation. Moreparticularly, FIG. 2 illustrates an HDL description of a port interfacethat can be used for disable circuit block 150 of FIG. 1. Like numberswill be used to refer to the same items throughout this specification.

Within port interface 200, the entity declaration for “disblk” indicatesthat the port interface includes a clock signal denoted as “clk,” aninput signal denoted as “in_signal,” an output signal denoted as“disable_signal,” and optionally an unlock key signal denoted as“unlock_key.” The disable signal can be used to selectively disabledifferent circuit elements within the circuit design into which disablecircuit block 150 is inserted. In one embodiment, the HLMS can couple“disable_signal” of port interface 200 incorporated into disable circuitblock 150 to components of circuit design 145 that, if disabled,effectively render evaluation circuit design 160 inoperable.

Within this specification, the same reference characters are used torefer to terminals, pins, wires, signal lines representing wires of acircuit design within an HLMS, and their corresponding signals. In thisregard, the terms “signal,” “wire,” “connection,” “terminal,” and “pin”may be used interchangeably, from time-to-time, within thisspecification. It also should be appreciated that the terms “signal,”“wire,” or the like can represent one or more signals, e.g., theconveyance of a single bit, or a plurality of bits sent serially,through a single wire or the conveyance of multiple parallel bitsthrough multiple parallel wires. Further, each wire or signal mayrepresent bi-directional communication between two, or more, elementsconnected by a signal or wire as the case may be.

FIG. 3 is second listing of program code illustrating an architecturaldescription 300 of a disable circuit block in accordance with anotherembodiment of the present invention. Architectural description 300,which in this example is specified in HDL, illustrates an example of thefunctionality and circuitry that can be specified by disable circuitblock 150.

As illustrated, the state of “disable_signal” can be defined in terms ofthe state of a counter that counts clock cycles. The term “n_clk”represents the count, and thus, the output signal of a counter thatcounts the number of rising clock edges encountered. While the value of“n_clk” is less than a predetermined value specified by the term “T,”“disable_signal” is set equal to “in_signal.” Thus, “in_signal” iseffectively passed as the output signal of disable circuit block 150while the term “n_clk” is less than the value specified for “T.” Whenthe term “n_clk” is greater than or equal to the term “T,”“disable_signal” is set to zero. Thus, when the value of “n_clk” exceedsthe value of “T,” the input signal is effectively zeroed in that thesignal output from disable circuit block 150, e.g., “disable_signal,” isno longer the same as “in_signal.”

Consider the case in which disable circuit block 150 is inserted on aclock enable signal. Thus, the input signal to disable circuit block 150is a clock enable signal. In the example pictured in FIG. 3, disablecircuit block 150 continues to output the clock enable signal as“disable_signal” while “n_clk” is less than the value specified by “T.”When “n_clk” is equal to, or exceeds, the value specified by “T,”“disable_signal” is set to zero. Thus, the clock enable signal is heldstatic, thereby disabling circuit elements that maintain state and arecoupled to the now disabled clock enable signal.

FIG. 4 is a second block diagram illustrating an unlock circuit block400 in accordance with another embodiment of the present invention. Theunlock circuit block 400 illustrated in FIG. 4 can be used in anembodiment in which the disable circuit block is permanently embeddedwithin the circuit design. In that case, the circuit design that isgenerated as the evaluation version and the “regular,” e.g.,non-evaluation version, can be identical. The evaluation circuit designcan be transformed into the “regular” circuit design through inclusionof unlock circuit block 400 within evaluation circuit design 160 and byproviding unlock circuit block 400, when instantiated within the IC,within a particular code that effectively overrides, e.g., disables,disable circuit block 150.

Unlock circuit block 400 illustrates an embodiment of an unlock circuitthat utilizes maximal codes and linear feedback shift registers (LFSRs).Unlock circuit block 400 includes a maximal length signal generator 405,a pre-initialized LFSR 410, a user key LFSR 415, exclusive OR 420, and aplurality of registers 425, 430, and 435. The user-supplied unlock keycan be provided through unlock key port 440 to LFSR 415. Unlock key port440 can be an input port at the top level of the circuit design withinwhich unlock circuit block 400 is to be inserted.

LFSR 410 can be pre-initialized with a maximal code length generated bymaximal length signal generator 405. The unlock key can be provided touser key LFSR 415 via unlock key port 440. If, and only if, the unlockkey, which in this case is the maximal code length passed topre-initialized LFSR 410, is passed into unlock key port 440, willexclusive OR 420 generate a constant stream of one that passes throughregisters 425-435 to output port 445.

In one embodiment, the signal generated by output port 445 can beprovided to enable the clock enable generator. In another embodiment,unlock circuit block 400 can be utilized in coordination with, orwithin, a disable circuit block, e.g., disable circuit block 150. In anycase, it should be appreciated that unlock circuit block 400 is providedas a non-limiting example of an unlock circuit or system that can beused within one or more of the embodiments described within thisspecification. As such, other unlock circuit blocks that utilize othertechnologies or techniques can be used in lieu of unlock circuit block400.

Disable hardware can be specified using any of a variety of differentformats that are understandable to, or that can be processed by, theHLMS. Disable hardware that conforms to a standardized interface, e.g.,the port interface illustrated in FIG. 2, also can be designed by ahardware designer. As illustrated, the disable hardware, whetherstandard circuit blocks that are part of the HLMS or a custom circuitdesign created by a designer, can be incorporated into a library ofcircuit blocks. In the event that the designer wishes to choose theparticular disable mechanism that is to be used, the designer ofevaluation circuit design 160 can select a disable circuit block alreadyincorporated within the library or provide an input specifying areference to a particular disable circuit block not included within thelibrary.

FIG. 5 is a block diagram of an evaluation circuit design in accordancewith another embodiment of the present invention. More particularly,FIG. 5 illustrates an example of evaluation circuit design 160 ofFIG. 1. Thus, the HLMS has selected a particular disable circuit blockand automatically inserted the disable circuit block within circuitdesign 145 to create evaluation circuit design 160. For ease ofillustration, data signals within circuit design 145 have been omitted.

In the example pictured in FIG. 5, the disable circuit blocks aredepicted as circuit blocks 520 and 525. Circuit blocks 520 and 525 havebeen selected and inserted on the clock enable signals that aregenerated by a clock enable generator 510 and provided to statefulelements of circuit design 145. Clock enable generator 510 is a standardcircuit block available within commercially available HLMSs thatgenerates clock enable signals. As shown, clock enable generator 510receives a clock signal from clock 505. Clock enable generator 510 canoutput a first clock enable signal from output “ce2” and a second clockenable signal from output “ce4”. Output “ce2” is coupled to the“in_signal” input of circuit block 520. Output “ce4” is coupled to the“in_signal” input of circuit block 525.

Without inclusion of circuit block 520, output “ce2” would be coupleddirectly to the clock enable “ce” input of each of circuit blocks 530,535, and 540 of circuit design 145. Similarly, without inclusion ofcircuit block 525, output “ce4” would be coupled directly to the clockenable “ce” input of each of circuit blocks 545, 550, and 555 of circuitdesign 145.

Each of circuit blocks 520 and 525 can incorporate aspects of theembodiments described within this specification with reference to FIGS.1-4. For example, circuit blocks 520 and 525 each can include a counterthat counts clock cycles on the clock signal generated by clock source505. While the count of the counter is less than the predeterminedthreshold “T,” the signal received at the “in_signal” input of each ofcircuit blocks 520 and 525 can be output from the “disable_signal”output of each of circuit blocks 520 and 525. When the count of thecounter is greater than or equal to the threshold “T,” the signal outputfrom the “disable_signal” output of each of circuit blocks 520 and 525can be a static signal that is held at zero, one, or some voltagebetween.

Each of circuit blocks 520 and 525 can include an input called“unlock_key” that is coupled to unlock key port 515, which is a portthrough which the unlock key can be provided to evaluation circuitdesign 160. As discussed, providing the unlock key to each of circuitblocks 520 and 525 can unlock evaluation circuit design 160 and overridethe disable mechanism included within each of circuit blocks 520 and525. As described, providing the unlock key to the “unlock_key” input ofeach of circuit blocks 520 and 525, overrides the disable mechanism andallows each of circuit blocks 520 and 525 to continue to output, fromthe “disable_signal” output, the signal received at the “in_signal”input regardless of whether the count of the counter is greater than orequal to the threshold “T.”

Accordingly, when each of circuit blocks 520 and 525 pass the signalreceived at input “in_signal” from the output “disable_signal,” circuitdesign 145 will continue to operate. When each of circuit blocks 520 and525 hold the signal output from output “disable_signal” static, circuitdesign 145 becomes inoperable, since stateful circuit blocks 520-555 canno longer operate.

FIG. 5 illustrates one technique for inserting disable circuit blocksinto a circuit design. In another embodiment, disable circuit blocks canbe inserted on reset signals. By keeping stateful elements of circuitdesign 145, whether most or all such elements, in a reset state,evaluation circuit design 160, when instantiated within an IC isrendered inoperable. In still another embodiment, disable circuit blockscan be inserted on data-in ports or data-out ports of circuit design145. For example, within selected HLMSs, a gateway in and/or a gatewayout block can be used to indicate the input port and output portrespectively of the programmable IC within which the evaluation circuitdesign will be instantiated. The gateway in and/or gateway out blockscan be located automatically with disable circuit blocks being insertedon one or more of the signals entering or leaving the ports representedby the gateway block(s).

In yet another embodiment, the HLMS can analyze circuit design 145 andidentify the top “N” nets, where N is an integer greater than zero,having the highest fanout. For example, if N=15, the 15 nets of circuitdesign 145 with the highest fanout can be identified. A disable circuitblock, as illustrated in FIG. 5, can be inserted into each of the Nnets. This process randomizes the location of the disable circuitblocks, thereby lowering the likelihood of an adverse party finding anddefeating the disable circuit blocks, within the actual hardwareimplementation of evaluation circuit design 160. Further, by placing thedisable circuit blocks on high fanout nets, the circuit design is morelikely to be disabled when the disable circuit blocks are activated.

FIG. 6 is a flow chart illustrating a method 600 of creating anevaluation version of a circuit design in accordance with anotherembodiment of the present invention. Method 600 can be performed by anHLMS as described with reference to FIGS. 1-5 of this specification.Accordingly, method 600 can begin in a state where a circuit design hasbeen implemented that is to be converted into an evaluation circuitdesign and evaluation hardware. In step 605, the circuit design can beloaded into the HLMS.

In step 610, the HLMS can select a particular type of disable circuitblock. In one embodiment, the HLMS can select the disable circuit blockthat is indicated or selected by the user. In another embodiment, theHLMS can select a particular type of disable circuit blockautomatically. For example, the particular type of disable circuit blockthat is selected can be one that does not include an unlock circuitblock or one that does include an unlock circuit block according topreviously established preferences.

Beginning in step 615, the HLMS can determine the technique to be usedto insert the disable circuit block into the circuit design. Theparticular technique selected also determines the location into whichthe disable circuit block, or blocks, as the case may be, is to beinserted into the circuit design for creation of the evaluation circuitdesign. For example, as discussed, disable circuit blocks can beinserted on clock enable signals, on input ports and/or output ports, oron the top “N” high fanout nets.

The HLMS can utilize different evaluation metrics for selecting aparticular technique. In one embodiment, the HLMS can determine thenumber of circuit elements that will be affected or rendered inoperablewithin the circuit design by each respective technique. The particulartechnique that renders the largest number of circuit blocks inoperablecan be selected. In another embodiment, the technique that results inthe fewest number of disable circuit blocks being inserted into thecircuit design can be selected. Thus, the HLMS can select the techniqueto be used in steps 615-630 based upon any combination of theaforementioned criteria, predetermined user preferences, or a directuser selection.

Accordingly, in step 615, the HLMS determines whether the disablecircuit block is to be inserted into the circuit design on clock enablesignals. If so, method 600 can continue to step 645. If not, method 600can proceed to step 620. Continuing with step 645, the HLMS can locateclock enable block(s) and select one or more clock enable signalsgenerated by the clock enable block(s). In step 650, a disable circuitblock can be inserted on each selected clock enable signal. In insertingthe disable circuit block(s), the HLMS can make any necessary signalconnections to and from each disable circuit block. After step 650,method 600 can proceed to step 680.

In step 620, the HLMS can determine whether the disable circuit block isto be inserted on an input port and/or an output port. If so, method 600can proceed to step 655. If not, method 600 can continue to step 625.Continuing with step 655, the HLMS can locate the input port or theoutput port, or both the input port and the output port of the circuitdesign. The HLMS can select either one or both of the input port andoutput port. In step 660, the HLMS can insert a disable circuit block onone or more or all signals of the selected port, whether clock or datasignals. In inserting the disable circuit block(s), the HLSM can makeany necessary signal connections to and from each disable circuit block.After step 660, method 600 can proceed to step 680.

In step 625, the HLMS can determine whether the disable circuit block isto be inserted on the top “N” high fanout nets. If so, method 600 canproceed to step 665. If not, method 600 can proceed to step 630.Continuing with step 665, the HLMS can sort nets of the circuit designaccording to fanout of each net. In step 670, the HLMS can select apredetermined number of nets, e.g., “N” nets, with the highest fanout.In step 675, the HLMS can insert a disable circuit block on eachselected net. For example, on a per net basis, the disable circuit blockcan be inserted after the source that outputs the high fanout outputsignal so that after insertion of the disable circuit block, each sinkof the high fanout signal of the high fanout net is driven by thedisable circuit block. As noted, inserting the disable circuit block(s)can include making any necessary signal connections to and from eachdisable circuit block. After step 675, method 600 can proceed to step680.

Continuing with step 630, the HLMS can determine that the disablecircuit block is to be inserted on reset signals of the circuit design.Accordingly, in step 635, the HLMS can locate one or more reset signalswithin the circuit design. In step 640, the HLMS can insert a disablecircuit block on each selected reset signal. In inserting the disablecircuit block(s), the HLMS can make any necessary signal connections toand from each disable circuit block. After step 640, method 600 canproceed to step 680.

In step 680, the HLMS can output the circuit design including theinserted disable circuit block(s) as an evaluation circuit design. Asused herein, “outputting” and/or “output” can mean, for example, writingto a file, writing to a user display or other output device, storing inmemory, sending or transmitting to another system, exporting, or thelike.

The embodiments disclosed within this specification provide for theautomated creation of evaluation circuit designs. The HLMS canautomatically select a particular circuit block, e.g., a disable circuitblock, for insertion into the circuit design that is to be transformedinto the evaluation circuit design. The disable circuit block(s)inserted into the circuit design prevent unauthorized use of the circuitdesign by third parties. Further, the HLMS can select the locationwithin the circuit design into which the disable circuit block is to beinserted.

The flowchart in the figures illustrates the architecture,functionality, and operation of possible implementations of systems,methods and computer program products according to various embodimentsof the present invention. In this regard, each block in the flowchartmay represent a module, segment, or portion of code, which comprises oneor more portions of executable program code that implements thespecified logical function(s).

It should be noted that, in some alternative implementations, thefunctions noted in the blocks may occur out of the order noted in thefigures. For example, two blocks shown in succession may, in fact, beexecuted substantially concurrently, or the blocks may sometimes beexecuted in the reverse order, depending upon the functionalityinvolved. It also should be noted that each block of the flowchartillustration, and combinations of blocks in the flowchart illustration,can be implemented by special purpose hardware-based systems thatperform the specified functions or acts, or combinations of specialpurpose hardware and executable instructions.

Embodiments of the present invention can be realized in hardware or acombination of hardware and software. The embodiments can be realized ina centralized fashion in one system or in a distributed fashion wheredifferent elements are spread across several interconnected systems. Anykind of data processing system or other apparatus adapted for carryingout the methods described herein is suited.

Embodiments of the present invention further can be embedded in a devicesuch as a computer program product, which comprises all the featuresenabling the implementation of the methods described herein. The devicecan include a data storage medium, e.g., a computer-usable orcomputer-readable medium, storing program code that, when loaded andexecuted in a system comprising memory and a processor, causes thesystem to perform the functions described herein. Examples of datastorage media can include, but are not limited to, optical media,magnetic media, magneto-optical media, computer memory such as randomaccess memory or hard disk(s), or the like.

The terms “computer program,” “software,” “application,”“computer-usable program code,” “program code,” “executable code,”variants and/or combinations thereof, in the present context, mean anyexpression, in any language, code or notation, of a set of instructionsintended to cause a system having an information processing capabilityto perform a particular function either directly or after either or bothof the following: a) conversion to another language, code or notation;b) reproduction in a different material form. For example, program codecan include, but is not limited to, a subroutine, a function, aprocedure, an object method, an object implementation, an executableapplication, an applet, a servlet, a source code, an object code, ashared library/dynamic load library and/or other sequence ofinstructions designed for execution on a computer system.

The terms “a” and “an,” as used herein, are defined as one or more thanone. The term “plurality,” as used herein, is defined as two or morethan two. The term “another,” as used herein, is defined as at least asecond or more. The terms “including” and/or “having,” as used herein,are defined as comprising, i.e., open language. The term “coupled,” asused herein, is defined as connected, whether directly without anyintervening elements or indirectly with one or more interveningelements, unless otherwise indicated. Two elements also can be coupledmechanically, electrically, or communicatively linked through acommunication channel, pathway, network, or system.

The embodiments disclosed herein can be embodied in other forms withoutdeparting from the spirit or essential attributes thereof. Accordingly,reference should be made to the following claims, rather than to theforegoing specification, as indicating the scope of the embodiments ofthe present invention.

1. A method of creating evaluation hardware within an integratedcircuit, the method comprising: determining, by a processor, a disabletechnique from a plurality of disable techniques according to anevaluation metric; automatically inserting, by the processor, a disablecircuit block into the circuit design; wherein the inserted disablecircuit block implements the determined disable technique; and storing,within a memory, the circuit design comprising the disable circuitblock.
 2. The method of claim 1, wherein the evaluation metric specifiesa number of circuit elements of the circuit design rendered inoperableby each disable technique.
 3. The method of claim 1, wherein theautomatically inserting comprises: automatically selecting a locationwithin the circuit design to insert the disable circuit block.
 4. Themethod of claim 3, wherein the automatically inserting furthercomprises: selecting at least one clock enable signal within the circuitdesign; and inserting the disable circuit block on each selected clockenable signal within the circuit design.
 5. The method of claim 3,wherein the automatically inserting further comprises: selecting atleast one of an input port or an output port within the circuit design;and inserting the disable circuit block on each selected port.
 6. Themethod of claim 3, wherein the automatically inserting furthercomprises: selecting a reset signal for at least one circuit elementthat stores state within the circuit design; and inserting the disablecircuit block on each selected reset signal.
 7. The method of claim 3,wherein the automatically inserting further comprises: sorting nets ofthe circuit design according to fanout; selecting a predetermined numberof nets with highest fanout; and inserting the disable circuit block onat least one signal of each selected net.
 8. The method of claim 1,wherein the evaluation metric specifies a number of disable circuitblocks inserted into the circuit design for each disable technique.
 9. Asystem that creates evaluation hardware, comprising: a memory storingprogram code; and a processor coupled to the memory and executing theprogram code, wherein the processor performs executable stepscomprising: determining a disable technique from a plurality of disabletechniques according to an evaluation metric; automatically inserting adisable circuit block into the circuit design; wherein the inserteddisable circuit block implements the determined disable technique; andstoring, within the memory, the circuit design comprising the disablecircuit block.
 10. The system of claim 9, wherein the evaluation metricspecifies a number of circuit elements of the circuit design renderedinoperable by each disable technique.
 11. The system of claim 9, whereinthe processor further performs an executable step comprising:automatically selecting a location within the circuit design to insertthe disable circuit block.
 12. The system of claim 11, wherein theautomatically inserting comprises: selecting at least one clock enablesignal within the circuit design; and inserting the disable circuitblock on each selected clock enable signal within the circuit design.13. The system of claim 11, wherein the automatically insertingcomprises: selecting at least one of an input port or an output portwithin the circuit design; and inserting the disable circuit block oneach selected port.
 14. The system of claim 11, wherein theautomatically inserting comprises: selecting a reset signal for at leastone circuit element that stores state within the circuit design; andinserting the disable circuit block on each selected reset signal. 15.The system of claim 11, wherein the automatically inserting comprises:sorting nets of the circuit design according to fanout; selecting apredetermined number of nets with highest fanout; and inserting thedisable circuit block on at least one signal of each selected net. 16.The system of claim 9, wherein the evaluation metric specifies a numberof disable circuit blocks inserted into the circuit design for eachdisable technique.
 17. A device, comprising: a data storage mediumusable by a system comprising a processor and a memory, wherein the datastorage medium stores program code that, when executed by the system,causes the system to execute operations comprising: automaticallyinserting a disable circuit block into the circuit design; wherein theautomatically inserting comprises: sorting nets of the circuit designaccording to fanout; selecting a predetermined number of nets withhighest fanout; and inserting the disable circuit block on at least onesignal of each selected net; and storing, within the memory, the circuitdesign comprising the disable circuit block.
 18. The device of claim 17,wherein the automatically inserting comprises: selecting at least oneclock enable signal within the circuit design; and inserting the disablecircuit block on each selected clock enable signal within the circuitdesign.
 19. The device of claim 17, wherein the automatically insertingcomprises: selecting at least one of an input port or an output portwithin the circuit design; and inserting the disable circuit block oneach selected port.
 20. The device of claim 17, wherein theautomatically inserting comprises: selecting a reset signal for at leastone circuit element that stores state within the circuit design; andinserting the disable circuit block on each selected reset signal.